• ISL6422B


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  • FileName: 000782.pdf [preview-online]
    • Abstract: 7. The EXTM1/2, SELVTOP1/2 TXT1/2 and ADDR0/1 pins have 200k internal pulldowns ... for the Rx mode the TXT1/2 is set low and the threshold is 400mV min in the Tx mode when TXT1/2 is set high. ...

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ISL6422B
Data Sheet April 25, 2007 FN6486.0
Dual Output LNB Supply and Control Features
Voltage Regulator with I2C Interface for • Single Chip Power solution
Advanced Satellite Set-Top Box Designs - True Dual Operation for 2-Tuner/2-Dish Applications
The ISL6422B is a highly integrated voltage regulator and - Both Outputs May be Enabled Simultaneously at
interface IC, specifically designed for supplying power and Maximum Power
control signals from advanced satellite set-top box (STB) - Integrated DC/DC Converter and I2C Interface
modules to the low noise blocks (LNBs) of two antenna • Switch-Mode Power Converter for Lowest Dissipation
ports. The device is consists of two independent current- - Boost PWMs with >92% Efficiency
mode boost PWMs and two low-noise linear regulators along - Selectable 13.3V or 18.3V Outputs
with the circuitry required for 22kHz tone generation, - Digital Cable Length Compensation (1V)
modulation and I2C device interface. The device makes the - I2C and Pin Controllable Output
total LNB supply design simple, efficient and compact with • Output Back Bias capability of 28V
low external component count. • I2C Compatible Interface for Remote Device Control
Two independent current-mode boost converters provide the • Four level Slave Address 0001 00XX
linear regulators with input voltages that are set to the final • 2.5V/3.3V/5V Logic Compatible
output voltages, plus typically 0.8V to insure minimum power • External Pins to Toggle between V and H polarization.
dissipation across each linear regulator. This maintains
• Built-In Tone Oscillator Factory Trimmed to 22kHz
constant voltage drops across each linear pass element
- Facilitates DiSEqC (EUTELSAT) Encoding
while permitting adequate voltage range for tone injection.
- External Modulation Input
The final regulated output voltages are available at two • Internal Over-Temperature Protection and Diagnostics
output terminals to support simultaneous operation of two • Internal OV, UV, Overload and Overtemp Flags (Visible on
antenna ports for dual tuners. The outputs for each PWM I2C)
can be controlled in two ways, full control from I2C using the
• FLT signal
VTOP1/2 and VBOT1/2 bits or set the I2C to the lower range
• LNB Short-Circuit Protection and Diagnostics
ie 13V/14V and switch to higher range ie 18V/19V with the
SELVTOP1/2 pin. All the functions on this IC are controlled • QFN and EPTSSOP Packages
via the I2C bus by writing 8 bits words onto the System • Pb-Free Plus Anneal Available (RoHS Compliant)
Registers (SR). The same register can be read back, and
four bits per output will report the diagnostic status. Separate Applications
enable commands sent on the I2C bus provide independent • LNB Power Supply and Control for Satellite Set-Top Box
standby mode control for each PWM and linear combination,
disabling the output into shutdown mode. Each output channel Ordering Information
is capable of providing 750mA of continuous current. The TEMP.
overcurrent limit can be digitally programmed. PART NUMBER PART RANGE PACKAGE PKG.
(Note) MARKING (°C) (Pb-Free) DWG. #
The External modulation input EXTM1/2 can accept a
ISL6422BERZ 6422BERZ -20 to +85 40 Ld 6x6 QFN L40.6x6
modulated Diseqc command and transfer it symetrically to
the output. Alternatively the EXTM1/2 pin can be used to ISL6422BERZ-T 6422BERZ -20 to +85 40 Ld 6x6 QFN L40.6x6
(Tape & Reel)
modulate the continous internal tone.
ISL6422BEVEZ 6422BEVEZ -20 to +85 38 Ld EPTSSOP M38.173B
The FLT pin serves as an interrupt for the processor when
ISL6422BEVEZ-T 6422BEVEZ -20 to +85 38 Ld EPTSSOP M38.173B
any condition turns OFF the LNB controller (Over
(Tape & Reel)
Temperature, Over Current, Disable). The nature of the fault
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
can be read of the I2C registers.
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6422B
Pinouts
ISL6422B
(38 LD EPTSSOP)
TOP VIEW
CS2 1 38 TXT2
VSW2 2 37 SELVTOP2
VSW2 3 36 TCAP2
GATE2 4 35 AGND
PGND2 5 34 VOUT2
EXTM2 6 33 TDIN2
SGND 7 32 TDOUT2
FLT 8 31 CPVOUT
SDA 9 30 CPSWOUT
SCL 10 29 CPSWIN
ADDR0 11 28 VCC
ADDR1 12 27 TDOUT1
EXTM1 13 26 TDIN1
BYP 14 25 VOUT1
PGND1 15 24 AGND
GATE1 16 23 TCAP1
VSW1 17 22 SELVTOP1
VSW1 18 21 NC
CS1 19 20 TXT1
ISL6422B
(40 LD 6X6 QFN)
TOP VIEW
SELVTOP2
PGND2
VOUT2
TCAP2
GATE2
AGND
VSW2
TXT2
CS2
NC
40 39 38 37 36 35 34 33 32 31
EXTM2 1 30 VOUT2
SGND 2 29 TDIN2
NC 3 28 TDOUT2
FLT 4 27 CPVOUT
SDA 5 26 CPSWOUT
SCL 6 25 CPSWIN
ADDR0 7 24 VCC
ADDR1 8 23 TDOUT1
EXTM1 9 22 TDIN1
BYP 10 21 VOUT1
11 12 13 14 15 16 17 18 19 20
GATE1
VSW1
SELVTOP1
TCAP1
PGND1
TXT1
NC
CS1
VOUT1
AGND
2 FN6486.0
April 25, 2007
Block Diagram
17 5 6 8 4 7
OLF1 OLF2
OVERCURRENT OVERCURRENT
SDA
SCL
ADDR1
ADDR0
COUNTER COUNTER
FLT
PROTECTION PROTECTION
SELVTOP1
LOGIC SCHEME 1 DCL1 DCL2 LOGIC SCHEME 2
OUVF1
OUVF2
PWM OC1 OC2 PWM
LOGIC LOGIC
GATE1 GATE2
12 Q CLK2 Q 39
CLK1
S S
SDA SCL ADDR1 ADDR0 OUVF2 PGND2
3
OUVF11 40
PGND1 ISEL1L&H ISEL2L&H
11 OLF1 FLT OLF2
EN1 EN2 - ILIM2 CS
+
I2 C AMP
ENT1 ENT2 CS2
INTERFACE ∑ 36
CS ILIM1 - OTF DCL
AMP + VTOP1 VBOT1 VBOT2 VTOP2
SLOPE
COMPENSATION
CS1
15 ∑
CLK1 OSC. CLK2
SLOPE 1.1MHz
COMPENSATION BAND GAP
REF VOLTAGE BGV
TDOUT1 BGV
23
ISL6422B
DIV AND -
+
- WAVE SHAPING REF
+
TONE REF VOLTAGE
DECODER TXT1 VOLTAGE ADJ2
ADJ1 VREF2
VREF1 INT
TDIN1 SELVTOP2
22 TONE 34
TONE TONE
INJ INJ
CKT 1 CKT 2 VSW2
VSW1 37
14
MSEL1
MSEL2
VO2
VO1 30,31
20,21 +
+ -
-
AGND
TXT2
19,32
EXT TONE CKT TDOUT2
28
VCC ON CHIP
24 LINEAR
TONE
UVLO DECODER
SGND POR ENT1 ENT2 TDIN2
2 SOFT-START 29
INT 5V
BYPASS
TXT1
THERMAL CPSWIN
TXT2
EXTM2
TCAP1
CHARGE PUMP
TCAP2
EXTM1
OTF 25
SOFT-START SHUTDOWN
EN1/EN2 CPVOUT CPSWOUT
16
April 25, 2007
10 18 9 1 33 35 27 26
FN6486.0
NOTE:
1. Pinouts shown are for the QFN package.
Typical Application Schematic QFN
2
1
L1
15uH
0
D1
CMS06
C5
56uF
PRELIMINARY 1
L4 4.7uH
2
D6 CMS06
1
L5 220uH
2
0
VIN
RTN
FLT BAR
SELVTOP2
TXT2
C3 C10 C11 C12 0 C25 0.22uF
56uF 10UF 10uF 10uF C19
VLNB2
4
R4 0.22uF R7 15
0 18 0 0 0 D7
C27 D4 C21 1.5KE24
0.1uF CMS06 0.1uF
RTN
0 0 0
1
2
3
R3 0
0
9
8
7
6
5
4
3
2
1
0
4
3
3
3
3
3
3
3
3
3
TPC6002 470 C23
Q3 10n R25 M7
C
C2
GD
TX 2
S2
S
R14 4.7K 10K NDS356 AP
A 2
N


Use: 0.0969